In recent years, in order to realize smaller and thinner electronic devices with high functionality and performance, high-density packaging techniques for semiconductor packages are demanded. As one of means for solving the problem, a substrate with built-in semiconductor element embedding a semiconductor element in the wiring substrate was proposed, and the research and development are underway. Meanwhile, as a circuit scale of a semiconductor element embedded in a wiring substrate is increased, the number of external connection terminals is increased, and the pitch between the external connection terminals is getting narrower. Patent Documents 1-3 describe conventional substrates with built-in semiconductor element embedding a semiconductor element.
FIG. 19 is a sectional view of a substrate with built-in semiconductor element described in Patent Document 1. There is provided a substrate with built-in semiconductor element (electronic device 1) of FIG. 19, in which wiring layers 10a-10c and electric insulating layers 9a-9d are stacked on a core substrate 2, and the wiring layers 10a-10c are made conductive to each other as desired by upper-and-lower conductive vias 7a-7d disposed in the electric insulating layers 9a-9d. In the electronic device 1, built-in electronic component layers 5A, 5B embedding electronic component(s) 8 are provided between the wiring layers 10a-10c or the core substrate 2 and the electric insulating layers 9a-9d. Terminal portions 8a of electronic components 8 are connected to wiring layers 10a, 10c through upper-and-lower penetrating vias 7. Meanwhile, Patent Document 1 describes only an embodiment in which a wiring layer and an electric insulating layer are disposed mainly on one side of the core substrate 2. However, Patent Document 1 describes that wiring layers, electric insulating layers and built-in electronic component layers may be formed on the two sides of the core substrate 2.
FIG. 20 is a sectional view of a semiconductor device mounting a semiconductor element (chip) 30 on one side of a core substrate 121, and having resin layers (insulating layers) 26a, 26b and wiring layers 27a, 27b on the two sides of the core substrate 121, which is described in Patent Document 2. Patent Document 2 describes that wirings can be drawn without increasing the number of wiring layers by providing a wiring layer 33 connected to an electrode pad 31 of the chip 30 on the chip 30 in advance using wafer-level packaging technique, and connecting the wiring layer 33 and the upper wiring layer 27 by via(s) VH1. Patent Document 2 describes a method for manufacturing the above-mentioned semiconductor device in which resin layers 26a, 26b are formed on two sides of the core substrate 121; after forming the resin layers on the two sides, via holes VH1, VH2 are formed on the two sides; shield layers are formed on the whole surfaces of the resin layers 26a, 26b including inner portions of the via holes VH1, VH2 respectively by means of electroless copper plating; after forming resist patterns on them, the via holes VH1, VH2 are filled up with a conductive material through electric field plating, and the wiring layer 27a of the top side and the wiring layer 27b of the bottom side are formed simultaneously.